In the production of integrated circuits on semi-conductor substrates, it is often necessary to selectively interconnect various doped zones or other different regions, connections or electrodes of the devices which are formed on the semi-conductor substrate. For example, in FET Technology, it is often necessary to connect selectively gate electrodes to source/drain diffusions or to connect different gate electrodes together, or to connect different source/drain regions together. In forming the devices, it is necessary to provide interconnections which connect selectively only those regions which are desired to be interconnected and to prevent connections of those regions which must be electrically isolated, and which during processing require steps or techniques which assure that they will not be interconnected.
The interconnection between the various zones or regions is desirably done by material which has a very high conductivity (i.e. a very low resistance). Thus, the interconnection should be done with materials that have very low resistivity so that minimal amounts of material can be used to provide the desired interconnection, and yet with these materials, the interconnections must be reliably made without shorting to undesired regions or without resulting opens or regions of high resistance within the interconnect lines or at the connections of the interconnect lines to the various regions.
There have been several prior art proposals for such type of interconnections, and included in these proposals is the use of various silicides such as has been shown in an article entitled HPSAC-A Silicided Amorphous-Silicon Contact and Interconnect Technology for VLSI by Wong, et al. in the IEEE transactions on electron devices in Vol. ED-34, No. 3, March 1987, 587-592. Also, a related technology using tungsten is disclosed in an article entitled A Selective CVD Tungsten Local Interconnect Technology by V. V. Lee, et al. in the International Electron Devices Meeting, Nichol Digest, 1988, Pages 450-453. Additionally, U.S. patent application Ser. No. 135,953 filed Dec. 21, 1987 entitled Method for Providing Bridge Contact Between Silicon Regions Separated By a Thin Dielectric, (IBM Docket No. BU9-87-034), and IBM Technical Disclosure Bulletin, Vol. 32, No. 9A, Pages 433-434 entitled Multi-Purpose Trench For a Complimentary Metal Oxide Silicon (CMOS), Six Device Static Random Access Memory (SRAM) Cell show the use of silicides as a strap for interconnection between spaced doped regions or connecting of polysilicon regions to doped regions. U.S. Pat. Nos. 4,714,951; 4,374,700; 4,873,204; 4,462,149; 4,463,491; and European Patent Publication No. 0046371 show the use of silicides in various configurations. Further, U.S. Pat. No. 4,745,081 shows a type of interconnect technology substrate contact with trench isolation areas. The article Titanium Nitride Local Interconnect Technology for VLSI by T. E. Tang et al. in IEEE Transactions on Electron Devices, Vol. Ed. 34, No. 3, March 1987 pp. 682-687, and report of 44th Annual Device Research Conference, Jun. 23-25, 1986; both show TiN technology for device interconnection.